Semiconductor structures with body contacts and fabrication methods thereof

ABSTRACT

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to commonly-assigned application Ser. No.______ filed on even date herewith, entitled “BODY-CONTACTEDSEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTEDSEMICONDUCTOR STRUCTURES” and bearing Attorney Docket No.ROC920050179US1, which is hereby incorporated by reference herein in itsentirety.

FIELD OF THE INVENTION

The invention relates generally to semiconductor structures and, inparticular, to semiconductor structures with multiple vertical memorycells arranged to form a memory array and methods of forming suchsemiconductor structures.

BACKGROUND OF THE INVENTION

Dynamic random access memory (DRAM) devices are the most commonly usedtype of semiconductor memory and, thus, are found in many integratedcircuit designs. DRAM devices are also frequently embedded intoapplication specific integrated circuits, such as processors and logicdevices. A generic DRAM device includes a plurality of substantiallyidentical semiconductor memory cell arrays, a plurality of bit lines,and a plurality of word lines that intersect the bit lines. Each memorycell array includes a plurality of memory cells arranged in rows andcolumns. Each individual memory cell in the array is located at theintersection of one of the word lines and one of the bit lines.

Each individual memory cell includes a storage capacitor for storingdata and an access device, such as a planar or vertical metal oxidesemiconductor field-effect transistor (MOSFET), for allowing thetransfer of data charges to and from the storage capacitor duringreading and writing operations. Either the source or drain of the accessdevice is connected to a corresponding bit line and the gate of theaccess device is connected to a corresponding word line. In certain DRAMdevice designs, memory cells are arranged in pairs to allow sharing of abit line contact, which significantly reduces the overall memory cellsize.

When the access device of one of the memory cells is activated by asignal on the word line, a data signal is transferred from the storagecapacitor of the memory cell to the bit line connected to the memorycell or from the bit line connected to the memory cell to the storagecapacitor of the memory cell. Because DRAM devices are a type ofvolatile memory that leaks stored charge, the data charge on the storagecapacitor (corresponding to a “1” or “0”) is periodically refreshedduring a refresh operation.

When data stored in one of the memory cells is read onto one of the bitlines, a potential difference is generated between the bit line of therespective memory cell and the bit line of another memory cell, whichform a bit line pair. A bit line sense amplifier connected to the dataline pair senses and amplifies the potential difference and transfersthe data from the selected memory cells to a data line pair.

One goal of memory device designers is to pack more memory cells moredensely into a smaller integrated circuit. Vertical memory cells featurean architecture in which the storage capacitor and access device arestacked vertically in a common trench. Vertical memory cells affordincreased packing densities and other advantages in comparison to planarmemory cells, in which size reduction was realized in the past primarilyby reduction of the linear dimensions (i.e., the minimum lithographicfeature size, F). For example, the packing density of vertical memorycells in a DRAM device is increased because the length of the verticalaccess device channel region is decoupled from the minimum lithographicfeature size. Consequently, vertical memory cells lack the scalingproblems with, for example, reducing the gate-oxide thickness andincreasing the channel doping concentration encountered when scalingplanar access devices to smaller sizes. The vertical memory cellarchitecture also allows longer channel lengths without a proportionaldecrease in memory density, as is true in planar memory cells. Channellength may also be properly scaled in vertical memory cells relative togate oxide thickness and relative to junction depth to reduce channeldoping, minimize junction leakage, and increase data retention times.

Constructing DRAM devices using semiconductor-on-insulator (SOI)technology offers many advantages over counterpart devices built in bulksemiconductor substrates including, but not limited to, higherperformance, absence of latch-up, higher packing density, and lowvoltage applications. In SOI technology, a thin semiconductor layer,often referred to as an SOI layer, is electrically isolated from athicker semiconductor substrate by an insulating or dielectric material,e.g., a buried oxide or BOX layer. The access devices for the memorycells are built in an SOI body defined as an electrically-isolatedsection of the SOI layer.

Floating body effects occur in vertical memory cells built using SOItechnology. SOI technology eliminates junction capacitance problemsobserved in comparable bulk devices by electrically isolating the SOIbody of transistor-type access devices from the underlying semiconductormaterial of the substrate. However, the SOI body may float at apotential that varies according to various conditions in which thetransistor-type access device is operated.

Floating body effects are known to significantly degrade cell dataretention time, which is most evident in long data retention time memorycells. Floating body effects originate from the accumulation of chargecarriers in the channel region of the access device defined in the SOIbody. A resultant leakage current is established via a parasitic bipolartransistor structure arising from the accumulated charge carriers. Ifuncompensated, the leakage current gradually discharges the storagecapacitor. Floating body effects also cause fluctuations in thethreshold voltage for the memory cell arising from the charge build up,which is extremely detrimental to the operation of transistor-typeaccess devices.

What is needed, therefore, is a semiconductor structure for an SOI DRAMcell array and a DRAM device with improved cell data retention times andmethods of fabricating such semiconductor structures that overcome thedisadvantages of conventional semiconductor structures and conventionalmethods of manufacturing such semiconductor structures, respectively.

SUMMARY OF THE INVENTION

The present invention is generally directed to asemiconductor-on-insulator (SOI) structure that incorporates a bodycontact extending through the buried dielectric layer and, thereby,coupling an SOI body with an underlying semiconductor substrate andmethods of forming such body contacts. The structure improves the celldata retention time for a vertical memory cell in an SOI dynamic randomaccess memory (DRAM) device by reducing floating body effects that, ifuncompensated, may affect the memory cell access device and result incharge loss from the associated storage capacitor in the vertical memorycell. Specifically, charge carriers that would otherwise accumulate inthe channel region of the access device are drained or dischargedthrough a leakage path, which may be high electrical resistance, definedby the body contact that extends to the underlying semiconductorsubstrate.

In accordance with one aspect of the present invention, a semiconductorstructure comprises a semiconductor wafer including a semiconductorsubstrate, a semiconductor layer with a plurality of semiconductorbodies, a buried dielectric layer separating the semiconductor substratefrom the semiconductor layer, and a plurality of memory cells built inan array on the semiconductor wafer. Each of the memory cells includes astorage capacitor and an access device. The access device has a verticalchannel region defined in one of the semiconductor bodies and a gateconfigured to switch current flow through the vertical channel region tothe storage capacitor. The structure further comprises a body contact ofan electrically conductive material extending through the burieddielectric layer. The body contact has a first end electricallyconnected with one of the semiconductor bodies and a second endelectrically connected with the semiconductor substrate.

In accordance with another aspect of the invention, a method is providedfor forming a semiconductor structure in a semiconductor wafer includinga semiconductor substrate, a semiconductor layer with a plurality ofsemiconductor bodies, a buried dielectric layer separating thesemiconductor substrate from the semiconductor layer, and a plurality ofmemory cells built in an array on the semiconductor wafer. A pluralityof trenches are etched in the semiconductor wafer and a vertical memorycell is built in each trench. The method further includes forming a viaextending through one of the semiconductor bodies and the burieddielectric layer and extending into the semiconductor substrate. Themethod further includes at least partially filling the via with a plugof an electrically conductive material that extends through the burieddielectric layer to define a body contact having a first endelectrically connected with the semiconductor body and a second endelectrically connected with the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments of the invention and,together with a general description of the invention given above and thedetailed description of the embodiments given below, serve to explainthe principles of the invention.

FIG. 1 is a top plan view of an array of vertical memory cells built ona portion of a semiconductor-on-insulator substrate in accordance withan embodiment of the invention.

FIG. 2 is a diagrammatic cross-sectional view of the substrate portionof FIG. 1 taken generally along lines 2-2.

FIGS. 3-12 are diagrammatic cross-sectional views similar to FIG. 2 ofthe substrate portion at various subsequent fabrication stages.

FIG. 13 is a diagrammatic cross-sectional view similar to FIG. 4 inaccordance with an alternative embodiment of the invention.

FIGS. 14-16 are diagrammatic cross-sectional views subsequent to thefabrication stage of FIG. 3 of the substrate portion at varioussubsequent fabrication stages in accordance with an alternativeembodiment of the invention.

FIGS. 17-19 are diagrammatic cross-sectional views subsequent to thefabrication stage of FIG. 3 of the substrate portion at varioussubsequent fabrication stages in accordance with an alternativeembodiment of the invention.

DETAILED DESCRIPTION

The present invention provides a semiconductor structure including anarray of vertical memory cells built using semiconductor-on-insulator(SOI) technology, as well as methods of making such semiconductorstructures. Specifically, the access device for at least one verticalmemory cell and, typically, every vertical memory cell in the memorycell array has an associated body contact, which may be high electricalresistance. Each body contact is established through the buriedinsulating or dielectric layer separating the floating SOI body of anSOI wafer, in which the access device is built, from the underlyingsemiconductor substrate. Although the invention is not so limited, thepresent invention may be particularly applicable and beneficial formerged isolation and node trench (MINT) memory cells. The presentinvention will now be described in greater detail by referring to thedrawings that accompany the present application.

With reference to FIGS. 1 and 2, a portion of a semiconductor wafer 10is shown that includes multiple substantially identical vertical memorycells, generally indicated by reference numeral 12, that are arranged inelectrically-isolated pairs of a considerably larger DRAM device builton semiconductor wafer 10. The larger DRAM device may constitute, but isnot limited to, a plurality of substantially identical memory cells 12each having a known eight square feature or 8F2 DRAM cell, as depictedin FIG. 1, and a plurality of substantially identical 8F2 DRAM cellsarranged in a larger array across the semiconductor wafer 10. A bit ofdata can be stored as a data charge in each of the individual 8F2 DRAMcells.

Before building the vertical memory cells 12, SOI semiconductor wafer 10comprises a semiconductor substrate 14, which is typically a singlecrystal or monocrystalline bulk silicon substrate, a buried insulatingor dielectric layer, illustrated as buried oxide (BOX) layer 18, and asemiconductor or SOI body 16 of a larger SOI layer separated from thesemiconductor substrate 14 by the intervening BOX layer 18. Thesubstrate 14 is doped with, for example, a p-type dopant across a layeror region 25 adjacent to the BOX layer 18. The SOI body 16, which isconsiderably thinner than the semiconductor substrate 14 and is alsotypically single crystal or monocrystalline silicon, is electricallyisolated from the semiconductor substrate 14 by the BOX layer 18. Thesemiconductor wafer 10 may be fabricated by any suitable conventionaltechnique, such as a wafer bonding technique or a separation byimplantation of oxygen (SIMOX) technique, familiar to persons ofordinary skill in the art.

Device isolation regions 20 (FIG. 1) are defined between adjacent rowsof vertical memory cells 12 in the cell array, such that the memorycells 12 are paired together. One specific pair of electrically-isolatedmemory cells 12 is shown in FIG. 2. These device isolation regions 20may be formed by, for example, a shallow trench isolation (STI)technique that includes a conventional lithography and dry etchingprocess to create trenches followed by filling the trenches with adielectric material, such as an oxide anisotropically deposited by ahigh density plasma (HDP) chemical vapor deposition (CVD) process, andthen planarization with a conventional chemical mechanical planarization(CMP) process. The device isolation regions 20 partition the SOI body 16into isolated active area regions or islands 15 on the BOX layer 18 and,thereby, assist in preventing carrier migration between adjacent memorycells 12. Each of the islands 15 may be considered to be used in theconstruction of a pair of memory cells 12 and, as a result, adjacentpairs of memory cells 12 do not share a common SOI body 16.

A relatively thin pad oxide layer 22 covers an upper horizontal surfaceof the SOI body 16. The pad oxide layer 22 may be oxide (SiO₂) depositedby a conventional thermal CVD process. A relatively thick pad nitridelayer 24 covers the pad oxide layer 22. The pad nitride layer 24 may becomposed of silicon nitride (Si₃N₄) formed by a conventional depositionprocess, such as CVD or plasma-assisted CVD.

Each of the vertical memory cells 12 is fabricated in a correspondingone of a plurality of trenches 26. Each of the trenches 26 extendsthrough the pad oxide and pad nitride layers 22, 24 and into thesemiconductor wafer 10 at locations dispersed across the surface ofwafer 10. More specifically, each trench 26, which is formed by aconventional lithography and etching process familiar to a person havingordinary skill in the art, extends through the SOI body 16 and the BOXlayer 18 and continues for a depth into region 25 of the semiconductorsubstrate 14 underlying the BOX layer 18.

Each memory cell 12 includes a storage capacitor 28, typically havingthe form of a deep trench (DT) capacitor, and an access device 30,typically having the form of a vertical metal oxide semiconductorfield-effect transistor, that are disposed within the trench 26 with avertically stacked arrangement. The access device 30 is electricallycoupled with the storage capacitor 28 for allowing the transfer of datacharges to and from the storage capacitor 28 during reading and writingoperations of the DRAM device. because the memory cells 12 aresubstantially identical, the constituent features of one pair of memorycells 12 will be described with the understanding that this descriptionapplies to all equivalent pairs of memory cells 12 in the memory cellarray and DRAM device.

The storage capacitor 28 of each vertical memory cell 12 is located in abottom or lower portion of the trench 26. The storage capacitor 28includes a capacitor node or plate 32 constituted by a conductor, suchas doped polycrystalline silicon (i.e., polysilicon). The capacitorplate 32, which includes a portion that projects vertically into the BOXlayer 18, is electrically isolated from the SOI body 16 by the BOX layer18. The capacitor plate 32 may be a heavily n-type doped region definedin the p-type region 25 of the semiconductor substrate 14.Alternatively, the capacitor plate 32 may be doped with a p-type dopantif region 25 is doped with an n-type dopant.

A buried capacitor plate 34 is present in the material of thesemiconductor substrate 14 bordering a lower portion of the trench 26.The buried capacitor plate 34 may be heavily doped with, for example, ann-type dopant within the p-type region 25 of the semiconductor substrate14. Alternatively, the buried capacitor plate 34 may be heavily dopedwith a p-type dopant if region 25 is doped with an n-type dopant. Buriedplate doping may be formed by conventional processes such asout-diffusing a dopant, such as the n-type dopant arsenic, from a layerof doped silicate glass on the sidewall of trench 26, gas phase doping,plasma doping, plasma immersion ion implantation, or any combination ofthese processes that are well known to a person having ordinary skill inthe prior art. Typically, the capacitor plates 32, 34 will be doped withthe same type of dopant.

A thin node dielectric 36, which lines the lower portion of trench 26,separates and electrically isolates the buried capacitor plate 34 fromcapacitor plate 32. The node dielectric 36 may be any suitabledielectric material, including but not limited to silicon oxide, siliconnitride, silicon oxynitride, aluminum oxide, combinations of thesedielectric materials, or another high-k material.

With continued reference to FIGS. 1 and 2, the access device 30 of eachvertical memory cell 12 is situated in a top or upper portion of thetrench 26 and, generally, is stacked vertically above the storagecapacitor 28. A trench-top insulator 38, which typically has the form ofa trench-top oxide, overlies the capacitor plate 32 vertically andelectrically isolates a vertical gate 40 of the access device 30 fromthe capacitor plate 32. Oxide for the trench-top insulator 38 may beformed in trench 26 above capacitor plate 32 by a suitable conventionalprocess, such as a HDP-CVD process. The vertical gate 40 is constitutedby an electrically conductive material, such as polysilicon deposited inthe upper portion of trench 26 using low-pressure CVD (LPCVD).

A buried deep strap connection 42 is provided in the BOX layer 18vertically between the vertical gate 40 and the capacitor plate 32. Alower source/drain region 44 of the access device 30 is defined bydopant outdiffusion from buried deep strap connection 42 that extendsinto the SOI body 16. The dopant in the lower source/drain region 44will be, for example, n-type if the dopant in the buried deep strapconnection 42 is n-type (e.g., arsenic, phosphorous, or antimony). Thesource/drain region 44 may operate either as the access device source oras the access device drain contingent upon the operation of accessdevice 30. Capacitor plate 32 of the storage capacitor 28 is tied to thelower source/drain region 44 of the access device 30 and buriedcapacitor plate 34 is tied to a reference potential or voltage. Theburied deep strap connection 42 electrically connects the capacitorplate 32 of the storage capacitor 28 through the lower source/drainregion 44 to a vertical channel region 64 (FIG. 9) of the access device30 when the vertical gate 40 is activated. A thin gate oxide 46, whichis formed in a conventional manner, is disposed on the vertical sidewallof trench 26 between the confronting sidewall of the vertical gate 40and the SOI body 16.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage, a hard masklayer 48 is applied to the pad nitride layer 24 and patterned with bodycontact vias 50 by any conventional lithography and etching techniquethat applies a resist layer (not shown), exposes the resist layer to apattern of radiation defined by a mask, develops the transferred patternin the exposed resist, and transfers the developed pattern to the hardmask layer 48 with a conventional anisotropic dry etching process, suchas reactive-ion etching (RIE) or plasma etching, that stops on the padnitride layer 24. The hard mask layer 48 may be oxide (SiO₂) depositedby a conventional thermal CVD process. An optional etch stop layer (notshown) of, for example, nitride may be provided between the hard masklayer 48 and the pad nitride layer 24 if the hard mask layer 48 issusceptible to removal during subsequent etching processes, as describedbelow. In this instance, the optional etch stop layer would mask thevertical gate 40 during the etching process.

Each of the body contact vias 50 is extended vertically through the padnitride layer 24 with a conventional anisotropic dry etching processthat stops on the pad oxide layer 22, through the pad oxide layer 22with another anisotropic dry etching process that stops on the SOI body16, through the SOI body 16 with another conventional anisotropic dryetching process that stops on the BOX layer 18, through the BOX layer 18with another conventional anisotropic dry etching process that stops onthe substrate 14, and into the wafer 10 with a final conventionalanisotropic etching process. The chemistry of each etching process,which may be conducted in a single etching step or multiple steps, ischosen according to the material selectivity required. Each of the etchprocesses relies on the hard mask layer 48 as an etch mask.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage, a spacer 52 ofa suitable semiconductor material, like silicon, is selectively formedwithin each of the body contact vias 50. The spacer 52, which isoptional, does not completely cover the entire sidewall of each via 50but is formed only on the exposed surfaces of the SOI body 16 and thesubstrate 14 that border each body contact via 50. These exposedsurfaces of the substrate 14 and the SOI body 16 operate as seeds forepitaxial growth of the optional spacer 52. The semiconductor materialforming the spacer 52 preferably does not form with an appreciablethickness on the vertical surfaces of the BOX layer 18, the pad oxidelayer 22, and the pad nitride layer 24 bordering each via 50.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage, a layer (notshown) of an electrically conductive fill material is deposited by aconventional process on hard mask layer 48. A body contact 54 is definedby a portion or plug of the deposited conductive fill material thatfills each via 50. An optional conventional planarization process, suchas chemical mechanical polishing (CMP), may be used to remove excessconductive fill material from hard mask layer 48, which re-exposes thehard mask layer 48. The planarization process stops vertically on theupper horizontal surface of hard mask layer 48. The body contact 54 maybe constituted by intrinsic polysilicon or n-type doped polysiliconformed within the p-type region 25 of the semiconductor substrate 14.Alternatively, the buried capacitor plate 34 may consist of p-type dopedpolysilicon if region 25 is doped with an n-type dopant.

The upper surface of the body contact 54 is recessed below thehorizontal level of the hard mask layer 48 by, for example, ananisotropic dry etch process that removes the constituent conductivefill material selective to the constituent material of the hard masklayer 48. In particular, the etch process recesses the body contact 54to a depth vertically above the depth of the BOX layer 18.

The presence of the spacer 52 effectively increases the spacing betweenthe body contact 54 and the buried deep strap connection 42 of theaccess device 30 by locally thickening the sidewall of trench 26. Thisdistances body contact 54 further away from the lower source/drainregion 44, which advantageously reduces the transfer of leakage currentto and from the buried deep strap connection 42 that is directlyconnected to capacitor plate 32 of the storage capacitor 28. If notabated, such leakage current may be detrimental to the operation of thevertical memory cell 12. Spacer 52 may be omitted if the proximity ofthe body contact 54 to the lower source/drain region 44 is not a concernin the device design.

Each body contact 54 electrically couples the SOI body 16 of the accessdevice 30 with the semiconductor substrate 14 to define a leaky currentpath therebetween. Each body contact 54 serves a pair of access devices30 in a contiguous island 15 of the monocrystalline semiconductordefined by the SOI body 16 on SOI wafer 10. If the body contact 54 isformed from doped polysilicon, the dopant type of the body contact 54should be the same as the dopant type in the SOI body 16 and thesubstrate 14 contacted by the body contact 54.

With reference to FIG. 6 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage, an insulatinglayer 56 is formed on the body contact 54. The insulating layer 56 maybe, for example, oxide deposited by a conventional HDP CVD oxideprocess, which deposits oxide on horizontal surfaces preferentially tovertical surfaces like trench sidewalls. Portions of the insulatinglayer 56 also cover the horizontal surface of hard mask layer 48. Anyportions of insulating layer 56 resident on the vertical sidewall of thebody contact via 50 above the body contact 54 are stripped by adirectional etch back process.

With reference to FIG. 7 in which like reference numerals refer to likefeatures in FIG. 6 and at a subsequent fabrication stage, a layer of afill material, such as intrinsic polysilicon or polysilicon dopedoppositely to the material (e.g., silicon) constituting the SOI body 16,is deposited by a conventional process on insulating layer 56. Thedopant type in plug 58 differs from the dopant type in body contact 54.For example, plug 58 may be polysilicon doped with a n-type dopant orintrinsic polysilicon if the body contact 54 is doped with a p-typedopant and the region 25 is also p-type.

A portion of the fill material fills each body contact via 50 with aplug 58 above the portion of the insulating layer 56 in via 50. Aconventional planarization process, such as CMP, is used to removeexcess fill material from the insulating layer 56 on the hard mask layer48, which re-exposes the insulating layer 56. The planarization processstops vertically on the upper horizontal surface of insulating layer 56.The upper surface of the plug 58 in each body contact via 50 is recessedby, for example, an anisotropic dry etch process that removes theconstituent fill material of plug 58 selective to the materialconstituting the hard mask layer 48. In particular, the etch processrecesses the plug 58 vertically to a depth within each body contact via50 approximately level with the pad oxide layer 22.

With reference to FIG. 8 in which like reference numerals refer to likefeatures in FIG. 7 and at a subsequent fabrication stage, the hard masklayer 48 and the insulating layer 56 are removed by a conventionalplanarization process, such as one or more CMP processes, that stopsvertically on the pad nitride layer 24. As a result, the respectiveupper surfaces of each vertical gate 40 and the pad nitride layer 24 areexposed.

With reference to FIG. 9 in which like reference numerals refer to likefeatures in FIG. 8 and at a subsequent fabrication stage, the padnitride layer 24 is stripped by an etch process that removes thematerial of the pad nitride layer 24 selective to the materialconstituting pad oxide layer 22. For example, a wet isotropic etchprocess using hot acid, such as phosphoric acid, may be employed toremove Si₃N₄ relative to oxide. An upper horizontal surface 60 of thepad oxide layer 22 is exposed after the pad nitride layer 24 is removed.The upper end of each conductive plug 58 projects vertically above thehorizontal level of surface 60.

An upper source/drain region 62 is defined by a doped region in an upperregion of the SOI body 16. For example, the upper source/drain region 62may be formed by implantation or diffusion of an n-type dopant, such asarsenic or phosphorous, into the SOI body 16 and plugs 58, if theseregions are doped with a p-type dopant. The upper source/drain region 62operates as either a source or a drain of the access device 30,contingent upon the operation of access device 30. The plug 58 in eachbody contact via 50 and portions of spacer 52 between each plug 58 andthe adjacent SOI body 16 participate, when doped, along with the SOIbody 16 to make the source/drain region 62 laterally continuous andunbroken. In particular, the interface between the doped plug 58 and theSOI body 16 make the source/drain region 62 continuous across the bodycontact 54 by bridging the body contact via 50.

A vertical channel region 64 is defined in the SOI body 16 near thevertical gate 40 and generally between the source/drain regions 44, 62of the access device 30. Current flowing through channel region 64between the source/drain regions 44, 62 is controlled or switched bypotential or voltage applied to the vertical gate 40. When the accessdevice 30 is switched “on” by application of a suitable voltage to thevertical gate 40, channel region 64 becomes electrically conductive toallow current flow between the source/drain regions 44, 62. The accessdevice 30 is considered by a person having ordinary skill in the art toconstitute a vertical device structure because of the three-dimensionalvertical arrangement of the vertical gate 40, the channel region 64, andthe source/drain regions 44, 62.

With reference to FIG. 10 in which like reference numerals refer to likefeatures in FIG. 9 and at a subsequent fabrication stage, the remnantsof pad oxide layer 22 are stripped utilizing a conventional etchingprocess that removes the material of layer 22 with a high selectively tothe material constituting the SOI body 16 (e.g., silicon). An array topinsulator 66 is formed on the source/drain region 62. The array topinsulator 66 may be formed, for example, by depositing oxide using aconventional HDP CVD oxide process and optionally planarizing with aconventional planarization process, such as a CMP process, that stopsvertically on the vertical gate 40. The body contact 54 is buried by thematerial of the array top insulator 66.

With reference to FIG. 11 in which like reference numerals refer to likefeatures in FIG. 10 and at a subsequent fabrication stage, a pluralityof word lines, including word lines 68, 70, 72 visible in FIG. 10, areformed by a series of processes familiar to a person having ordinaryskill in the art. The array top insulator 66 operates to electricallyisolate the source/drain region 62 from word lines 68, 70, 72. Each ofthe word lines 68, 70, 72 consists of one or more conducting layersconstituted by a conductor, such as polysilicon, tungsten nitride (WN),tungsten (W), tungsten silicide (WSi), or layered combinations of thesematerials. Each of the word lines 68, 70, 72 includes anelectrically-insulating cap 74 of, for example, nitride stationed atopthe conducting layer(s), and electrically-insulating sidewall spacers 76of, for example, nitride flanking the conducting layer(s).

Word line 68 is electrically coupled with the storage capacitor 28 ofone vertical memory cell 12 visible in FIG. 11 by the underlying accessdevice 30. A potential applied from word line 68 to vertical gate 40controls the data charge on the storage capacitor 28 by selectivelytransferring current between the source/drain regions 44, 62 through thecorresponding channel region 64 in the SOI body 16. Similarly, word line72 is electrically coupled with the storage capacitor 28 of the othermemory cell 12 visible in FIG. 11 by the underlying access device 30. Apotential applied from word line 72 to the vertical gate 40 of theaccess device 30 of this memory cell 12 likewise controls the datacharge on the corresponding storage capacitor 28 by selectivelytransferring current between the source/drain regions 44, 62 through thecorresponding channel region 64 in the SOI body 16.

To provide the electrical coupling, the vertical gate 40 of each accessdevice 30 for the exemplary pair of vertical memory cells 12 visible inFIG. 11 is contacted by one of the word lines 68, 72. As a consequence,these word lines 68, 72 are referred to as active word lines. The otherword line 70 does not contact either of the memory cells 12 visible inFIG. 11 and is referred to as a passing word line. This word line 70,which is passing in FIG. 11, is connected with the access device 30 inother memory cells 12 in the memory cell array (FIG. 1) and in the DRAMdevice. Similarly, word lines 68, 72, which are active in FIG. 11, arenot connected with the access device 30 of certain other memory cells 12in the memory cell array (FIG. 1) and in the DRAM device. Consequently,as appreciated by a person having ordinary skill in the art, ascribingthe terms active and passing to the word lines 68, 70, 72 depends uponwhich specific pair of word lines 68, 70, 72 is coupled with eachelectrically-isolated pair of memory cells 12 in the memory cell arrayand DRAM device. The body contact via 50 and body contact 54 are formedin a region of the SOI semiconductor wafer 10 that directly underliesthe passing word line 70.

With reference to FIG. 12 in which like reference numerals refer to likefeatures in FIG. 11 and at a subsequent fabrication stage, a layer 78 ofa suitable gap fill material, such as oxide or borophosphosilicate glass(BPSG) is deposited and planarized to fill gaps between adjacent pairsof word lines 68, 70, 72. The material of the gap fill layer 78 isplanarized by a conventional planarization process, such as a CMPprocess, to establish an upper horizontal surface by relying on caps 74as a polish stop.

Bit line contacts 80, each consisting of a conductive material likemetal or polysilicon, are then formed using conventional bit lineformation techniques. Each bit line contact 80 extends through the gapfill layer 78 to establish an electrical contact with the correspondingsource/drain region 62. For example, the bit line contacts 80 may beformed by depositing a resist layer on gap fill layer 78, patterning theresist layer to form a bit line contact pattern, etching the unmaskedregions of the gap fill layer 78 by an etching process that removes theconstituent material of layer 78 selective to the constituent materialof SOI body 16 to form bit line contact vias to the source/drain region62, removing the resist layer, depositing a blanket layer of aconductive material suitable for forming contacts 80, and planarizingwith a conventional process, like a CMP process, to the top of the gapfill layer 78.

Normal processing is used to complete the DRAM integrated circuit, asunderstood by a person having ordinary skill in the art. Normalprocessing may include, but is not limited to, deposition of aninterlayer dielectric (not shown) such as BPSG or another suitableinsulator, formation of bit lines (not shown) that contact the bit linecontacts 80, and formation of higher level metallizations (not shown)and insulating layers (not shown).

With reference to FIG. 13 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage in accordancewith an alternative embodiment of the present invention, the insulatinglayer 56 is formed on the body contact 54 by a conventional thermal CVDprocess, such as an oxide CVD process. Portions of the insulating layer56 also cover the horizontal surface of hard mask layer 48. Theinsulating layer 56 overlying the body contact 54 is recessed by anappropriate process to a depth approximately level with pad oxide layer22. For example, the insulating layer 56 may be recessed using an oxidewet (HF-based) etch or a dry RIE process appropriate to etch an oxideconstituting insulating layer 56. The process that recesses theinsulating layer 56 covering the body contact 54 also removes theresidue of layer 56 on the hard mask layer 48 (FIG. 5) and also removesthe remnants of the hard mask layer 48.

Processing continues with the fabrication stage of FIG. 8 by depositinga fill material, such as intrinsic polysilicon or doped polysilicon(e.g., n⁺ polysilicon), similar to the material constituting the SOIbody 16 on pad nitride layer 24 and planarizing with a conventionalplanarization process, such as a CMP process, that stops vertically onthe upper horizontal surface of pad nitride layer 24, to form plugs 58.The upper surface of each plug 58 is recessed by, for example, ananisotropic dry etch process that removes the constituent fill materialof plug 58 selective to the constituent material of the hard mask layer48. In particular, the etch process recesses the plug 58 vertically to adepth approximately level with the pad oxide layer 22.

With reference to FIG. 14 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage in accordancewith another alternative embodiment of the present invention, a regionor plug 82 of a material, such as intrinsic polysilicon or polysilicondoped similar to the material (e.g., silicon) constituting the substrate14, is formed in each of the body contact vias 50. For example, plug 82may be heavily doped with a p-type dopant if region 25 of the substrate14 has a p-type conductivity. The plug 82 may be formed in each bodycontact via 50 by depositing a blanket layer of the constituentmaterial, planarizing with a conventional process, such as CMP, thatstops vertically on the hard mask layer 48, and etching with, forexample, an anisotropic dry etch process that removes the materialconstituting plug 82 selective to the constituent material of hard masklayer 48. The etching process recesses the upper surface of the plug 82inside each body contact via 50 vertically to a depth below theinterface between the SOI body 16 and the BOX layer 18.

With reference to FIG. 15 in which like reference numerals refer to likefeatures in FIG. 14 and at a subsequent fabrication stage, the spacer 52is selectively formed within each of the body contact vias 50 and coversthe exposed sidewalls of the SOI body 16. However, instead of lining thebody contact via 50 at a level below the interface between the substrate14 and BOX layer 18, a portion of the spacer 52 nucleates on the uppersurface of plug 82 and covers plug 82 with an overlying relationship.

With reference to FIG. 16 in which like reference numerals refer to likefeatures in FIG. 15 and at a subsequent fabrication stage, anotherregion or plug 84 is formed in each of the body contact vias 50 abovethe portion of the spacer 52 covering plug 82. Plug 84 may be formedfrom the same material and by a similar process as plug 82. For example,the plug 84 may be intrinsic polysilicon or polysilicon heavily dopedwith a p-type dopant if plug 82 is intrinsic polysilicon or polysiliconheavily doped with a p-type dopant. The plug 84 may be formed in each ofthe body contact vias 50 by depositing a blanket layer of theconstituent material, planarizing with a conventional process, such asCMP, that stops vertically on the hard mask layer 48, and etching with,for example, an anisotropic dry etch process that removes theconstituent material of plug 84 selective to the constituent material ofhard mask layer 48. The upper surface of the plug 84 in each bodycontact via 50 is recessed vertically by the etching process such thatthe upper surface of plug 84 is at a depth above the interface betweenthe SOI body 16 and the BOX layer 18 and below the interface between theSOI body 16 and the pad oxide layer 22.

The plugs 82, 84 in each of the body contact vias 50 and the portion ofthe spacer 52 between the plugs 82, 84 collectively constitute aconductive structure that operates as a body contact equivalentfunctionally to the body contact 54 (FIG. 5). Processing continues inthis alternative embodiment beginning at the fabrication stage shown inFIG. 6.

With reference to FIG. 17 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage in accordancewith yet another alternative embodiment of the present invention, aregion or plug 86 of a material, such as intrinsic polysilicon orpolysilicon doped similar to the material (e.g., silicon) constitutingthe substrate 14, is formed in each of the body contact vias 50. Forexample, the plug 86 may be heavily doped with a p-type dopant if region25 of the substrate 14 has a p-type conductivity. The plugs 86 may beformed by depositing a blanket layer of the constituent material,planarizing with a conventional process, such as a CMP process, thatstops vertically on the hard mask layer 48, and etching with, forexample, an anisotropic dry etch process that removes the constituentmaterial of plug 86 selective to the constituent material of hard masklayer 48. The upper surface of each plug 86 is recessed vertically bythe etch process such that the upper surface of plug 86 is at a depthbelow the interface between the SOI body 16 and the BOX layer 18.

Next, an isolation spacer or collar 88 of an insulating or dielectricmaterial is formed on the exposed sidewall of each body contact via 50by a conventional process. For example, isolation collar 88 may beformed from oxide deposited by a conformal CVD process and etched usinga dry etching process, such as an RIE, that removes the constituentmaterial of the isolation collar 88 selective to the materialconstituting the plug 86.

With reference to FIG. 18 in which like reference numerals refer to likefeatures in FIG. 17 and at a subsequent fabrication stage, a region orplug 90 of a material similar or identical to the material constitutingplug 86 is formed in each body contact via 50 to define a cap above plug86. For example, the plug 90 may be polysilicon heavily doped with ap-type dopant if plug 86 is polysilicon also heavily doped with a p-typedopant. Similar to plug 86, plug 90 may be formed in each body contactvia 50 by deposited by depositing a blanket layer of the constituentmaterial, planarizing with a conventional process, such as CMP, thatstops vertically on the hard mask layer 48, and etching with, forexample, an anisotropic dry etch process that removes the constituentmaterial of plug 90 selective to the constituent material of hard masklayer 48. The upper surface of the plug 90 in each of the body contactvias 50 is recessed vertically by the etching process such that theupper surface of plug 90 is at a depth above the interface between theSOI body 16 and the BOX layer 18.

A portion of the isolation collar 88 projecting vertically above theplug 90 is removed by an etch process, such as a wet isotropic etchprocess, that removes the material of isolation collar 88 selective tothe material constituting plug 90. The etching process is continued torecess the isolation collar 88 vertically below the upper surface ofplug 90. Plug 90 lies within the body contact via 50 at a locationradially inside of the isolation collar 88.

With reference to FIG. 19 in which like reference numerals refer to likefeatures in FIG. 18 and at a subsequent fabrication stage, a region orplug 92 of a material similar to the material constituting plugs 86 and90 is formed in each body contact via 50 above plug 90. For example,plug 92 may be heavily doped with a p-type dopant if plugs 86 and 90 arepolysilicon heavily doped with a p-type dopant. Similar to plugs 86 and90, plug 92 may be formed in each body contact via 50 by depositing ablanket layer of the constituent material, planarizing with aconventional process, such as CMP, that stops vertically on the hardmask layer 48, and etching with, for example, an anisotropic dry etchprocess that removes the constituent material of plug 92 selective tothe constituent material of hard mask layer 48. The upper surface ofplug 92 is recessed vertically by the etch process such that the uppersurface of plug 92 is at a depth below the interface between the SOIbody 16 and the pad oxide layer 22.

The plugs 86, 90, 92 collectively constitute a body contact that isstructurally equivalent functionally to the body contact 54 (FIG. 5).Specifically, plug 86 is electrically coupled with the substrate 14,plug 92 is electrically coupled with the SOI body 16, and plug 90electrically couples plug 86 with plug 92 to structurally comprise thebody contact 54. Processing continues in this alternative embodimentbeginning at the fabrication stage shown in FIG. 6.

The isolation collar 88 provides an intervening structure that preventsany interactions between the material of the SOI body 16 and the bodycontact 54 defined by plugs 86, 90, 92 and effectively provides a bufferregion so that the SOI body 16 and the body contact 54 lack aninterface. This is particularly beneficial in situations in which theSOI body 16 is single crystal silicon and the plugs 86, 90, 92 areconstituted by polysilicon because defects in the polysilicon tend topropagate into the single crystal silicon. The isolation collar 88 alsooperates to distance the plugs 86, 90, 92 from the buried deep strapconnection 42.

It should be noted that embodiments of the present invention aredescribed herein with semiconductor structures being doped for aparticular device type, i.e. n-type FET's (N-channel FET's). However,the invention is not so limited as a person having ordinary skill wouldunderstand how to replace N-channel FET's with p-type FET's (P-channelFET's) and n-type dopant with p-type dopant (e.g., boron or indium)where appropriate without departing from the spirit or scope of theinvention.

The present invention provides various advantages in comparison with theconstruction of conventional DRAM cell arrays. In particular, thepresent invention provides for ultra-scalable and high performance SOIvertical array DRAM device having a high-resistance body contact topotentially eliminate and, at the least, significantly reduce thefloating body effect by providing a conduction or leakage path throughthe BOX layer 18 from the SOI body 16 to the semiconductor substrate 14.The beneficial result is that the leakage current from storage capacitor28, arising from diffusion of charge carriers to this interface, issignificantly reduced. The present invention is compatible with thecurrent DRAM and enhanced dynamic random access memory (eDRAM)processes. The present invention is easy to implement in a circuitdesign and cost-effective, which is beneficial for purposes ofmanufacturability.

References herein to terms such as “vertical”, “horizontal”, etc. aremade by way of example, and not by way of limitation, to establish aframe of reference. The term “horizontal” as used herein is defined as aplane parallel to the conventional plane or surface of semiconductorwafer 10, before processing and regardless of the actual spatialorientation of semiconductor wafer 10. The term “vertical” refers to adirection perpendicular to the horizontal, as just defined. Terms, suchas “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”,“over”, “beneath” and “under”, are defined with respect to thehorizontal plane. It is understood that various other frames ofreference may be employed for describing the present invention withoutdeparting from the spirit and scope of the present invention.

The fabrication of the semiconductor structure herein has been describedby a specific order of fabrication stages and steps. However, it isunderstood that the order may differ from that described. For example,the order of two or more fabrication steps may be switched relative tothe order shown. Moreover, two or more fabrication steps may beconducted either concurrently or with partial concurrence. In addition,various fabrication steps may be omitted and other fabrication steps maybe added. It is understood that all such variations are within the scopeof the present invention. It is also understood that features of thepresent invention are not necessarily shown to scale in the drawings.

While the present invention has been illustrated by a description ofvarious embodiments and while these embodiments have been described inconsiderable detail, it is not the intention of the applicants torestrict or in any way limit the scope of the appended claims to suchdetail. Additional advantages and modifications will readily appear tothose skilled in the art. Thus, the invention in its broader aspects istherefore not limited to the specific details, representative apparatusand methods, and illustrative examples shown and described. Accordingly,departures may be made from such details without departing from thespirit or scope of applicants' general inventive concept.

1. A semiconductor structure comprising: a semiconductor wafer includinga semiconductor substrate, a semiconductor layer with a plurality ofsemiconductor bodies, and a buried dielectric layer separating saidsemiconductor substrate from said semiconductor layer; a plurality ofmemory cells built in an array on said semiconductor wafer, each of saidmemory cells including a storage capacitor and an access device, andsaid access device including a vertical channel region defined in one ofthe semiconductor bodies and a gate configured to switch current flowthrough said vertical channel region to said storage capacitor; and abody contact of an electrically conductive material extending throughsaid buried dielectric layer, said body contact having a first endelectrically connected with one of said semiconductor bodies and asecond end electrically connected with said semiconductor substrate. 2.The semiconductor structure of claim 1 further comprising: aninsulator-filled trench electrically isolating a pair of said memorycells from adjacent memory cells in said array, said body contactextending substantially through said dielectric layer between said pairof said memory cells.
 3. The semiconductor structure of claim 2 furthercomprising: a first word line electrically coupled with said gate of oneof said pair of said memory cells; and a second word line positionedbetween said pair of said memory cells, said body contact being alignedvertically with said second word line.
 4. The semiconductor structure ofclaim 1 further comprising: a via extending through said semiconductorbody and said buried dielectric layer and into said semiconductorsubstrate, said via being partially filled by said body contact; and asidewall spacer with said via and separating said body contact from thecorresponding one of said semiconductor bodies.
 5. The semiconductorstructure of claim 4 wherein said access device of each of said memorycells further includes a source/drain region electrically coupled withsaid storage capacitor, and said sidewall spacer is positioned betweensaid source/drain region and said body contact.
 6. The semiconductorstructure of claim 5 wherein said sidewall spacer comprises an isolationcollar of an insulating material.
 7. The semiconductor structure ofclaim 6 wherein said body contact includes a first region and a secondregion spaced within said via by said isolation collar from said firstregion.
 8. The semiconductor structure of claim 7 wherein said bodycontact includes a third region electrically coupling said first andsecond regions and positioned within said via inside said isolationcollar.
 9. The semiconductor structure of claim 1 wherein saidsemiconductor body is formed from a semiconductor material, and furthercomprising: a via extending through the corresponding one of saidsemiconductor bodies and the buried dielectric layer and extending intothe semiconductor substrate, said body contact being positioned withinsaid via; an insulating layer within said via and overlying said bodycontact; and a plug of said semiconductor material within said via andseparated from said body contact by said insulating layer, said plugfilling said via such that said semiconductor body has an interface withthe semiconductor body.
 10. The semiconductor structure of claim 9wherein said access device of each of said memory cells further includesa source/drain region electrically coupled by said vertical channelregion with said storage capacitor when said gate is switched to permitcurrent flow through said vertical channel region to said storagecapacitor, said source/drain region extending into said semiconductorbody and into said plug.
 11. The semiconductor structure of claim 1wherein each of said memory cells comprises an eight square featuredynamic random access memory (DRAM) memory cell.
 12. A method forforming a semiconductor structure in a semiconductor wafer including asemiconductor substrate, a semiconductor layer with a plurality ofsemiconductor bodies, and a buried dielectric layer separating thesemiconductor substrate from the semiconductor layer, the methodcomprising: building a plurality of vertical memory cells each in acorresponding one of a plurality of trenches in the semiconductor wafer;forming a via extending through one of the semiconductor bodies and theburied dielectric layer and extending into the semiconductor substrate;and at least partially filling the via with a plug of an electricallyconductive material that extends through the buried dielectric layer todefine a body contact having a first end electrically connected with thesemiconductor body and a second end electrically connected with thesemiconductor substrate.
 13. The method of claim 12 wherein the verticalmemory cells further include a first vertical memory cell and a secondvertical memory cell adjacent to the first vertical memory cell, andfurther comprising: forming an insulating layer on the semiconductorbody; and building a plurality of word lines on the semiconductor waferincluding a first word line on the insulating layer between the firstand second memory cells and electrically isolated from the first andsecond memory cells, the first word line aligned vertically with thebody contact.
 14. The method of claim 13 wherein the plurality of wordlines further includes a second word line connected with an accessdevice of the first vertical memory cell and a third word line connectedwith an access device of the second vertical memory cell, the second andthird word lines electrically isolated from the first word line.
 15. Themethod of claim 12 further comprising: forming a sidewall spacer withinthe via that separates the body contact from the semiconductor body. 16.The method of claim 15 wherein forming the sidewall spacer furthercomprises: forming an epitaxial layer on a portion of the semiconductorbody bordering the via.
 17. The method of claim 15 wherein forming thesidewall spacer further comprises: forming an isolation collar of aninsulating material on a portion of the semiconductor body bordering thevia and surrounding a portion of the body contact.
 18. The method ofclaim 12 further comprising: forming an insulating layer in the viaabove the body contact; and forming a plug of semiconductor materialwithin the via and on the insulating layer, the plug having an interfacewithin said via with the semiconductor body.
 19. The method of claim 18wherein each of the vertical memory cells includes an access device witha first source/drain region and a storage capacitor electrically coupledby the first source/drain region with the access device, and furthercomprising: introducing a dopant into the semiconductor body and theplug of semiconductor material to define a second source/drain regionfor the access device of each of the vertical memory cells.
 20. Themethod of claim 18 wherein the body contact is doped with aconcentration of a p-type dopant and the semiconductor material in theplug is doped with a concentration of an n-type dopant.
 21. The methodof claim 12 wherein each of the vertical memory cells includes a storagecapacitor and an access device with a vertical channel region defined inone of the semiconductor bodies and a gate configured to switch currentflow through the vertical channel region to the storage capacitor. 22.The method of claim 12 wherein forming the via further comprises:etching the via into the semiconductor wafer.